The assignee of the present application has introduced a family of ASICs that are based on a predefined fabric of logic cells and memories that form a configurable base (or “slice”). The silicon containing this “slice” is processed up to a predefined layer, such as metal 1, to be customized or configured later to provide the desired functionality as per customer specifications, using subsequent levels of vias and metals. This reduces non-recurring costs as well as turnaround time for chip designs. To provide the maximum flexibility as well as utilization of the “pre-diffused” circuitry, it is necessary to use designs that are easily configurable to provide the desired functionality using metal levels only.
Application Ser. No. 10/431,940, entitled “Metal Programmable Single-Port SRAM Array For Dual-Port Functionality,” provides such a configurable design for providing dual-port capability to an SRAM array. The SRAM array is first fabricated with single port memory cells up to the metal 1 layer. Thereafter, the single port SRAM cells are configured using upper levels of metallization to provide customized multiport capability, as shown in FIG. 1.
FIG. 1 is a diagram illustrating an SRAM array comprising conventional single-port cells and split word lines. Each single-port cell 700 comprises six transistors that form a flip-flop circuit for storing data, which is formed by cross-coupling two logic inverters formed by transistors Q1D–Q4D, and two pass-gate transistors Q5D and Q6D. The source and drain of pass-gate transistor Q5D are connected between bit lines 720 and node 706D. The source and drain of pass-gate transistor Q6D are connected between inverse bit lines 728 and node 710D. Unlike a single word-line memory circuit, SRAM array 600 uses two word lines per row, word lines 724 and 730, each of which is connected to only one of the pass-gate transistors. Word line 724 is connected to the gate terminal of pass-gate transistor Q5D, and word line 730 is connected to the gate terminal of pass-gate transistor Q6D. In normal single port operation, data can be written to, or read from, each cell by asserting corresponding word and bit lines.
FIG. 1 also shows how two or more split word memory cells, such as cells 700 and 702 of the same row, can be connected in the array and metal-programmed to function as a dual-port memory cell. Internal node 706D of memory cell 700 is connected to internal node 706E of memory cell 702 via metal connection 704. Internal node 710D of memory cell 700 is connected to internal node 710E of memory cell 702 via metal connection 708. Connecting these corresponding internal nodes together forms a dual-port memory cell from the two single-port memory cells 700 and 702. The first port is made up of bit lines 720 and 722 and word line 724, which are connected to pass-gate transistors Q5D and Q6E. The second port is made up of bit lines 726 and 728 and word line 730, which are connected to pass-gate transistors Q6D and Q5E.
Using split word lines with metal programming as shown in FIG. 1 allows a dual-port memory cell to be assembled from only two single-port memory cells, which saves a significant amount of layout space compared to a situation where the base array is made of dual port cells. However, it would also be useful to have an additional degree of configurability wherein a given array of cells can be broken into multiple, smaller sub-arrays (or instances), each of which can be configured as single port (1P), dual port (2P), or multi-port in general. The “break points” in the array where the sub-arrays are separated must be configurable and flexible. In addition, the break points must be configurable in such a manner as to render an unused sub-array incapable of impacting the remaining (targeted) functional sub-arrays. The present invention addresses such needs.